Current integrated circuit (IC) design flows are broken into several functions. Design teams typically focus on synthesis, place and route, layout versus schematic (LVS), timing closure, power closure, reliability closure, and design rule checking (DRC). The “GDS-II” database is signed off and released to a post-design processing team which applies various forms of RET (resolution enhancement techniques), mainly OPC (optical proximity correction). OPC is done on pre-defined masking layers, usually using lithographic models provided by the wafer fab. Each mask layer of the whole chip is run through OPC with the appropriate model, then released to the mask shop for fracturing and mask making.
In today's era of sub-wavelength photolithography, in which the feature sizes are smaller than the wavelength of the exposure light, the full-chip OPC creates patterns for the masks which are difficult to validate for correctness. A number of electronic design automation (EDA) tools are trying to perform “hot spot” checks or design rule checking (DRC) on the full-chip post-OPC databases. Sheer data volumes make this difficult, as the post-OPC databases can be 20 to 100 times larger than the original layout. Therefore, full-chip OPC can be extremely expensive in terms of cost and schedule. Also, OPC done on the full chip at this phase of the design flow is in the critical path for getting the database to the mask shop. Additionally, complete circuit checking after full-chip OPC (prior to fabrication) is difficult if not impossible. Therefore, some problems cannot be identified until the design is fabricated on wafer, thereby resulting in significant financial and time-to-market risk.
As part of the timing closure, extraction tools combine the full-chip layout information based on idealized polygon shapes with a wafer fab technology file to add parasitic components to the circuit schematic. Since the as-fabricated features on the wafer do not exactly match the idealized polygon shapes defined in the layout, geometric dependent parasitics like resistances and capacitances are less accurate than may be needed, thereby creating a potential for error in timing analysis.